1. Field of the Invention
This invention relates to an improved, dielectrically isolated structure for use in SOI-type semiconductor devices, in particular, in intelligent power devices.
2. Description of the Related Art
FIGS. 1A through FIG. 1D are a process flowchart explaining of the manufacturing a completely dielectrically-isolated substrate for use in an SOI-type semiconductor device, which is now under study. The process comprises four steps, i.e., trench-forming, corner-rounding, embedding, and levelling.
In the trench-forming step shown in FIG. 1A, an oxide film 12, having a thickness of about 1.5 .mu.m, is formed on a silicon (Si) substrate 11. Then, the substrate 11, covered with the film 12, and another silicon (Si) substrate 13 are bonded together by means of wafer-bonding technique. The substrate 13 is abraded by a grinder or the like, thus obtaining a desired thickness of, e.g. 20.+-.5 .mu.m. Subsequently, a masking layer 14, made of SiO.sub.2 and being about 2.3 .mu.m thick, is applied over the substrate 13. Thereafter, PEP (Photo Etching Process) is performed. Specifically, the silicon substrate 13 is etched by RIE (Reactive Ion Etching), thereby forming a trench 15 extending to the oxide film 12 and having a width of about 2.0 .mu.m.
In the corner-rounding step shown in FIG. 1B, the corners of the side walls of the trench 15 are rounded by, for example, CDE (Chemical Dry Etching) using CF.sub.4 (freon).
In the embedding step shown in FIG. 1C, the chip is thermally oxidized at about 1050.degree. C. in the atmosphere of oxygen, thereby forming an oxide film 17 on the side wall of the trench 15. Then, a polysilicon film 16 is deposited over the entire surface of the chip by the use of, for example, CVD (Chemical Vapour Deposition) under a reduced pressure of 1 Torr or less. At this time, the polysilicon film 16 is embedded in the trench 15.
In the levelling step shown in FIG. 1D, the etchback of the polysilicon film 16 is performed by, for example, the aforementioned CDE, thus levelling the surface of the silicon substrate 13. Thereafter, an oxide film is applied over the entire surface of the substrate 13, thereby obtaining a dielectrically isolated substrate.
In the above-described steps, it is most important to minimize crystal defect occurring at the corners of the bottom of the trench 15. To this end, the corner-rounding process is provided, as is shown in FIG. 1B.
FIG. 2A shows the shape of a trench formed in a dielectrically isolated substrate manufactured by a process including no corner-rounding steps. FIG. 2B shows the shape of a trench formed in a dielectrically isolated substrate manufactured through a process including a corner-rounding step shown in FIG. 1B.
The dielectrically isolated substrate shown in FIG. 2B has trenches each having its bottom, formed by the oxide film 12, undercut. In the embedding step after the oxidization of the side walls of the trenches, a polysilicon film 16 is deposited on the entire surface of the chip, whereby the trenches 15 are completely filled with polysilicon. Thus, the corners of the trench bottom, formed by the oxide film 12, are completely filled with polysilicon, which reduces crystal defect occurring at the corners.
However, it is known that even the above-described dielectrically isolated substrate does not have a sufficiently high breakdown voltage.
FIGS. 3A and 3B show manners of measuring the breakdown voltage of such a dielectrically isolated substrate, and FIG. 3C shows the measurement results.
It is considered that the thickness of the oxide film 17, formed on the side walls of a trench, greatly affects the breakdown voltage of the dielectrically isolated substrate. Hence, we prepared substrates having side-wall films 17 of thicknesses of 4000, 6000, and 8000 .ANG.. We then measured the breakdown voltage between the adjacent element regions in each substrate, as is shown in FIG. 3A, and that between a base plate and element regions in each substrate, as is shown in FIG. 3B.
As can be understood from FIG. 3C, the breakdown voltage obtained is proportional to the thickness of the side-wall oxide film 17, and lower than each of the values required for the substrates of the given thicknesses. Specifically, only a breakdown voltage of about 600 V was obtained from the substrate having trenches each insulated by a bottom oxide film 12 of 1.6 .mu.m, and a side-wall oxide film 17 of 0.8 .mu.m (=8000 .ANG.) (accordingly, the sum thickness of the films formed on the both side walls of a trench is 16000 .ANG.).
However, in this case, the breakdown voltage must be, in theory, at least about 1400 V.